Revision Standard - Inactive-Withdrawn.Administratively withdrawn January 2007 A common bus architecture (which includes functional components--modules, nodes,and units--and their address space, transaction set, CSRs, and configuration information) suitable for both parallel and serial buses is provided in this standard. Bus bridges are enabled by the archi-tecture, but their details are beyond its scope. Configuration information is self- administered byvendors and organizations based upon IEEE Registration Authority company_id.
address space; architecture; bus; computer; CSR; interconnect; microprocessor; register; transaction set
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