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Normas IEEE americanas electrotécnicas - AENOR

IEEE 1076.3-1997

Fecha:
1997-06-05 /Inactive-Superseded
Título:
IEEE Standard VHDL Synthesis Packages
Scope:

New IEEE Standard - Superseded.
The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.

Keywords:

interpretations; metalogical values; numeric VHDL vector types; signed; synthesis; unsigned

120,27
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Formato físico y digital

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