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Normas IEC internacionales electrotécnicas - AENOR
IEC 61691-6:2009

IEC 61691-6:2009

Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions

Fecha:
2009-12-14 /Vigente
Resumen (inglés):
IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.
Resumen (francés):
323
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