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Normas BSI – AENOR
BS IEC 61691-4:2004

BS IEC 61691-4:2004

Behavioural languages. Verilog hardware description language

Fecha Anulación:
2012-04-20 /Withdrawn
Comité:
EPL/501
Equivalencias internacionales:

IEC 61691-4:2004

Resumen:
Contains the formal syntax and semantics of all Verilog HDL constructs; the formal syntax and semantics of Standard Delay Format (SDF) constructs; simulation system tasks and functions,such as text output display commands; compiler directives,such as text substitution macros and simulation time scaling; the Programming Language Interface (PLI) binding mechanism; the formal syntax and semantics of access routines,task/function routines,and Verilog procedural interface routines; informative usage examples; informative delay model for SDF; listings of header files for PLI This publication has the status of a double logo IEEE/IEC standard
Keywords:
Computer applications, Design, Programming languages, Mathematical calculations, Data processing equipment, Computer hardware, Data processing
682,8
Idioma Formato

Formato digital

Nota: Precios sin IVA ni gastos de envío

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