Test Method for Estimating Electromigration Median Time-To-Failure and Sigma of Integrated Circuit Metallizations
1.1 This test method is designed to characterize the failure distribution of interconnect metallizations such as are used in microelectronic circuits and devices that fail due to electromigration under specified d-c current-density and temperature stress. This test method is intended to be used only when the failure distribution can be described by a log-Normal distribution.
1.2 This test method is intended for use as a referee method between laboratories and for comparing metallization alloys and metallizations prepared in different ways. It is not intended for qualifying vendors or for determining the use-life of a metallization.
1.3 The test method is an accelerated stress test of four-terminal structures (see Guide F1259) where the failure criterion is either an open circuit in the test line or a prescribed percent increase in the resistance of the test structure.
1.4 This test method allows the test structures of a test chip to be stressed while still part of the wafer (or a portion thereof) or while bonded to a package and electrically accessible via package terminals.
1.5 This test method is not designed to characterize the metallization for failure modes involving short circuits between adjacent metallization lines or between two levels of metallization.
1.6 This test method is not intended for the case where the stress test is terminated before all parts have failed.
1.7 This standard may involve hazardous materials, operations, and equipment. This standard does not purport to address all of the safety problems associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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